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[Other resource] 结合XILINXCPLD RS232通信(verilog)

Description: 结合XILINXCPLD所做的模拟RS232通信verilog源程序-XILINXCPLD combine the simulation RS232 communication Verilog source
Platform: | Size: 122378 | Author: 于飞 | Hits:

[Com Port] RS232

Description: FPGA实现RS-232串口收发的Verilog程序，已经调通。
Platform: | Size: 2180 | Author: 鲁东旭 | Hits:

[Other resource] rs232

Description: RS232 verilog design
Platform: | Size: 114650 | Author: liuKe | Hits:

[ELanguage] async_transmitter

Description: 用verilog实现rs232通信async_transmitter.v-with verilog achieve rs232 communications async_transmitter.v
Platform: | Size: 1024 | Author: weixing | Hits:

[ELanguage] async_receiver

Description: 用verilog实现rs232 receiveri -with verilog achieve rs232 receiveri
Platform: | Size: 1024 | Author: weixing | Hits:

[VHDL-FPGA-Verilog] uart

Description: 用Verilog实现的串口异步通信，适用于RS232-Using Verilog realization of serial asynchronous communication, applied to RS232
Platform: | Size: 1126400 | Author: 王权 | Hits:

[Com Port] b13c_environment

Description: rs232控制器，实现rs232的环境设置，verilog编写，所有权归opencores-rs232 controller rs232 to achieve the environmental settings, verilog prepared, owned by opencores
Platform: | Size: 63488 | Author: uknow | Hits:

[VHDL-FPGA-Verilog] EPM240Prj

Description: 这是一个verilog HDL 语言的例子，在CPLD器件EPM240上实现了 RS232协议、按键处理、LED数码管显示和每秒加1数码显示。使用quartus ii 7.0 以上打开.-This is an example of verilog HDL language in the CPLD device EPM240 achieved RS232 agreement, deal button, LED digital tube display and digital display plus 1 per second. Quartus ii 7.0 use more than open.
Platform: | Size: 521216 | Author: 白蚁 | Hits:

[Parallel Port] cw3

Description: serial port rs232 in verilog source code
Platform: | Size: 1024 | Author: malkanin | Hits:

[Embeded-SCM Develop] c_FPGA

Description: RS232设计，硬件测试通过，VERILOG实现的，比较好的哦-RS232 design, hardware test, VERILOG realized, oh good
Platform: | Size: 1249280 | Author: 洪依 | Hits:

[VHDL-FPGA-Verilog] uart1

Description: RS232(UART)串口传输，通过了FPGA验证功能正确-UART RS232 verilog HDL FPGA xilinx
Platform: | Size: 237568 | Author: 徐 | Hits:

[VHDL-FPGA-Verilog] RS232_control

Description: verilog RS232信号解码模块。为在FPGA中的verilog代码。-verilog RS232 control module。
Platform: | Size: 10240 | Author: haohuifeng | Hits:

[VHDL-FPGA-Verilog] rs232-Quartus

Description: 利用verilog語法,來達成串口rs232的功能-Using verilog syntax, to achieve the functions of serial rs232
Platform: | Size: 480256 | Author: 張三 | Hits:

[VHDL-FPGA-Verilog] Verilog000

Description: FPGA的学习，熟悉QuartusII软件的各种功能，各种逻辑算法设计，接口模块(RS232,LCD,VGA,SPI,I2c等)的设计，时序分析，硬件优化等，自己开始设计简单的FPGA板子。 ③、NiosII的学习，熟悉NiosII的开发流程，熟悉开发软件(SOPC,NiosII IDE),了解NiosII的基本结构，设计NiosII开发板，编写NiosII C语言程序，调试板子各模块功能。-Verilog语言的学习，熟悉Verilog语言的各种语法。 ②、FPGA的学习，熟悉QuartusII软件的各种功能，各种逻辑算法设计，接口模块(RS232,LCD,VGA,SPI,I2c等)的设计，时序分析，硬件优化等，自己开始设计简单的FPGA板子。 ③、NiosII的学习，熟悉NiosII的开发流程，熟悉开发软件(SOPC,NiosII IDE),了解NiosII的基本结构，设计NiosII开发板，编写NiosII C语言程序，调试板子各模块功能。
Platform: | Size: 22794240 | Author: onejacky | Hits:

[VHDL-FPGA-Verilog] RS232

Description: It s combination logic for UART. edited in verilog-HDL
Platform: | Size: 1024 | Author: kim | Hits:

[VHDL-FPGA-Verilog] URAT

Description: Verilog硬件描述语言，RS232串口发送接收程序-Verilog hardware description language, RS232 serial port send and receive program
Platform: | Size: 1024 | Author: zhaoyf | Hits:

[VHDL-FPGA-Verilog] async_receiver

Description: verilog语言，RS232异步接收和发送模块-verilog language, RS232 asynchronous receive and transmit modules
Platform: | Size: 1024 | Author: 何沐 | Hits:

[Other] FPGA-rs232(verilog)-2

Description: FPGA rs232串口收发程序，3个程序任意选择，全部可用-FPGA rs232 serial transceiver procedures, three procedures arbitrarily selected, all available
Platform: | Size: 100352 | Author: xy | Hits:

[VHDL-FPGA-Verilog] RS232

Description: 基于quartusii的用verilog编写的rs232串口程序(QuartusII based on Verilog prepared by the RS232 serial procedures)
Platform: | Size: 948224 | Author: qiaodecheng | Hits:

[VHDL-FPGA-Verilog] serialtest

Description: rs232 serialtest in verilog
Platform: | Size: 112640 | Author: Ni Ni | Hits:
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